In order to program an EPROM MOS memory transistor, both the gate and drain terminals must be connected to a special high supply voltage VPP, typically 15 volts compared with the typical 5 volts of the normal supply voltage VDD.
In known arrangements the VPP supply voltage is coupled to the drain of the memory transistor via a load line controlled by address lines which include high voltage driver transistors.
The load line control arrangement has been implemented by high voltage CMOS inverters including P-channel and N-channel transistors in which the P-channel transistors require BVDSS breakdown protection. In addition the separation between such P-channel and N-channel transistors in the high voltage section takes up a greater area of silicon, which results in a design which does not have a compact silicon implementation.
This invention seeks to provide a memory transistor programming arrangement which requires only N-channel transistors and in which the above mentioned problems are mitigated.